# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s

--- |
  define arm_aapcs_vfpcc void @test_vqrshruntq_n_s32(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) {
  entry:
    %cmp = icmp slt i32 %elts, 1
    br i1 %cmp, label %exit, label %loop.ph

  loop.ph:                                          ; preds = %entry
    %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)
    br label %loop.body

  loop.body:                                        ; preds = %loop.body, %loop.ph
    %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]
    %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]
    %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]
    %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]
    %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]
    %pred = call <4 x i1> @llvm.arm.mve.vctp32(i32 %count)
    %elts.rem = sub i32 %count, 4
    %masked.load.a = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.a, i32 4, <4 x i1> %pred, <4 x i32> undef)
    %masked.load.b = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %addr.b, i32 4, <4 x i1> %pred, <4 x i32> undef)
    %bitcast.a = bitcast <4 x i32> %masked.load.a to <8 x i16>
    %shrn = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> %bitcast.a, <4 x i32> %masked.load.b, i32 3, i32 1, i32 0, i32 1, i32 0, i32 1)
    %bitcast = bitcast <8 x i16> %shrn to <4 x i32>
    call void @llvm.masked.store.v4i32.p0(<4 x i32> %bitcast, ptr %addr.c, i32 4, <4 x i1> %pred)
    %addr.a.next = getelementptr <4 x i32>, ptr %addr.a, i32 1
    %addr.b.next = getelementptr <4 x i32>, ptr %addr.b, i32 1
    %addr.c.next = getelementptr <4 x i32>, ptr %addr.c, i32 1
    %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)
    %end = icmp ne i32 %loop.dec, 0
    %lsr.iv.next = add i32 %lsr.iv, -1
    br i1 %end, label %loop.body, label %exit

  exit:                                             ; preds = %loop.body, %entry
    ret void
  }

  define arm_aapcs_vfpcc void @test_vqrshruntq_n_s16(ptr %a, ptr %b, ptr %c, i32 %elts, i32 %iters) {
  entry:
    %cmp = icmp slt i32 %elts, 1
    br i1 %cmp, label %exit, label %loop.ph

  loop.ph:                                          ; preds = %entry
    %start = call i32 @llvm.start.loop.iterations.i32(i32 %iters)
    br label %loop.body

  loop.body:                                        ; preds = %loop.body, %loop.ph
    %lsr.iv = phi i32 [ %lsr.iv.next, %loop.body ], [ %start, %loop.ph ]
    %count = phi i32 [ %elts, %loop.ph ], [ %elts.rem, %loop.body ]
    %addr.a = phi ptr [ %a, %loop.ph ], [ %addr.a.next, %loop.body ]
    %addr.b = phi ptr [ %b, %loop.ph ], [ %addr.b.next, %loop.body ]
    %addr.c = phi ptr [ %c, %loop.ph ], [ %addr.c.next, %loop.body ]
    %pred = call <8 x i1> @llvm.arm.mve.vctp16(i32 %count)
    %elts.rem = sub i32 %count, 8
    %masked.load.a = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %addr.a, i32 2, <8 x i1> %pred, <8 x i16> undef)
    %masked.load.b = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %addr.b, i32 2, <8 x i1> %pred, <8 x i16> undef)
    %bitcast.a = bitcast <8 x i16> %masked.load.a to <16 x i8>
    %shrn = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> %bitcast.a, <8 x i16> %masked.load.b, i32 1, i32 1, i32 0, i32 1, i32 0, i32 1)
    %bitcast = bitcast <16 x i8> %shrn to <8 x i16>
    call void @llvm.masked.store.v8i16.p0(<8 x i16> %bitcast, ptr %addr.c, i32 2, <8 x i1> %pred)
    %addr.a.next = getelementptr <8 x i16>, ptr %addr.b, i32 1
    %addr.b.next = getelementptr <8 x i16>, ptr %addr.b, i32 1
    %addr.c.next = getelementptr <8 x i16>, ptr %addr.c, i32 1
    %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)
    %end = icmp ne i32 %loop.dec, 0
    %lsr.iv.next = add i32 %lsr.iv, -1
    br i1 %end, label %loop.body, label %exit

  exit:                                             ; preds = %loop.body, %entry
    ret void
  }

  declare i32 @llvm.start.loop.iterations.i32(i32)
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
  declare <4 x i32> @llvm.masked.load.v4i32.p0(ptr, i32 immarg, <4 x i1>, <4 x i32>)
  declare void @llvm.masked.store.v4i32.p0(<4 x i32>, ptr, i32 immarg, <4 x i1>)
  declare <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16>, <4 x i32>, i32, i32, i32, i32, i32, i32)
  declare <8 x i1> @llvm.arm.mve.vctp16(i32)
  declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)
  declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32 immarg, <8 x i1>)
  declare <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8>, <8 x i16>, i32, i32, i32, i32, i32, i32)

...
---
name:            test_vqrshruntq_n_s32
alignment:       2
tracksRegLiveness: true
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  restorePoint:    ''
fixedStack:
  - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: test_vqrshruntq_n_s32
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
  ; CHECK:   tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
  ; CHECK: bb.1.loop.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3
  ; CHECK:   renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
  ; CHECK:   dead $lr = MVE_DLSTP_32 killed renamable $r3
  ; CHECK:   $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg
  ; CHECK: bb.2.loop.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r12
  ; CHECK:   $lr = tMOVr $r12, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 4)
  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 4)
  ; CHECK:   renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg
  ; CHECK:   renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 4)
  ; CHECK:   dead $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3.exit:
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r4, -8
    tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate

  bb.1.loop.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $lr

    renamable $r4 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
    $lr = t2DoLoopStart renamable $r4
    $r12 = tMOVr killed $r4, 14 /* CC::al */, $noreg

  bb.2.loop.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $r0, $r1, $r2, $r3, $r12

    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg, $noreg
    $lr = tMOVr $r12, 14 /* CC::al */, $noreg
    renamable $r12 = t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
    MVE_VPST 4, implicit $vpr
    renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 4)
    renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 4)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    renamable $q1 = MVE_VQSHRUNs32th killed renamable $q1, killed renamable $q0, 3, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $r2 = MVE_VSTRWU32_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 4)
    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.exit:
    tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc

...
---
name:            test_vqrshruntq_n_s16
alignment:       2
tracksRegLiveness: true
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
fixedStack:
  - { id: 0, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: test_vqrshruntq_n_s16
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
  ; CHECK:   tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
  ; CHECK: bb.1.loop.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3
  ; CHECK:   renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
  ; CHECK:   dead $lr = MVE_DLSTP_16 killed renamable $r3
  ; CHECK:   $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg
  ; CHECK: bb.2.loop.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r4
  ; CHECK:   $lr = tMOVr $r4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.addr.b, align 2)
  ; CHECK:   renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 0, $noreg, $noreg :: (load (s128) from %ir.addr.a, align 2)
  ; CHECK:   $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg
  ; CHECK:   renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.addr.c, align 2)
  ; CHECK:   dead $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3.exit:
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r4, -8
    tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r4, def $pc, implicit killed $itstate

  bb.1.loop.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $lr

    renamable $r12 = t2LDRi12 $sp, 8, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
    $lr = t2DoLoopStart renamable $r12
    $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg

  bb.2.loop.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $r0, $r1, $r2, $r3, $r4

    renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
    $lr = tMOVr $r4, 14 /* CC::al */, $noreg
    renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
    MVE_VPST 4, implicit $vpr
    renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.b, align 2)
    renamable $q1 = MVE_VLDRHU16 killed renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.addr.a, align 2)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    $r0 = tMOVr $r1, 14 /* CC::al */, $noreg
    renamable $q1 = MVE_VQSHRUNs16th killed renamable $q1, killed renamable $q0, 1, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $r2 = MVE_VSTRHU16_post killed renamable $q1, killed renamable $r2, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.addr.c, align 2)
    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.exit:
    tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc

...
